育才学习网1.怎么写verilog 测试程序
给你写一个例子，下面是一个设计文件和一个对应的测试程序，希望能起到抛砖引玉的和用：
/*
File Name : test.v
Author : t()
)
endmodule
module counter(
input wire clk,
input wire rst_n,
output reg [3:0]cnt
);
always@(posedge clk or negedge rst_n)
if(~rst_n)
cnt<='d0;
else
cnt<=cnt+4'd1;
endmodule
4.用verilog编写源代码和测试程序
下面的代码我已经用modelsim仿真过了，没有问题。
module count(out,clk,rst)； //源程序
input clk,rst;
output[3:0] out;
reg[3:0] out;
initial out=4'd0;
always @(posedge clk or negedge rst)
begin
if(!rst) out=4'd0;
else
begin
out=out+4'd1;
if(out==4'd1||out==4'd6||out==4'd8) out=out+4'd1;
if(out==4'd5) out=out+4'd2;
end
end
endmodule
`timescale 1ns/1ns //测试程序
`include "count.v"
module count_tp;
reg clk,rst;
wire[3:0] out;
parameter DELY=100;
count mycount(out,clk,rst);
always #(DELY/2) clk=~clk;
initial
begin
clk=0;rst=1;
#(DELY*5) rst=0;
#DELY rst=1;
#(DELY*20) $finish;
end
initial $monitor($time,,,"clk=%d rst=%d out=%d",clk,rst,out);
endmodule
5.Verilog 测试文件怎么写
module test_freq;
// Inputs
reg [3:0] a,b;
reg ci;
// Outputs
wire [3:0] y;
wire co;
// Instantiate the Unit Under Test (UUT)
add4bit uut (
.a(a),
.b(b),
.ci(ci),
.co(co),
.y(y)
);
initial begin
// Initialize Inputs
a= 0;
b= 0;
ci= 0;
// Wait 100 ns for global reset to finish
#100;
a = 3;
b=4;
ci =0;
end
endmodule
如上就是测试3+4，进位为0时的输出。测试的步骤网上看看吧，各个软件不一样。
6.怎样用verilog语言写测试文件
`timescale 1ps/1ps
module sim();
reg clk,rst,in;
wire out;
initial
begin
clk <= 0;
rst <= 0;
in <= 0;
#10
rst <= 1;
end
always #25 clk <= ~clk;
always
begin
#(372162-50)
in <= 1;
#50
in <= 0;
end//373134
fill U (clk,rst,in,out);
endmodule
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